Micron to bond NAND wafers for 2027 launch

Micron announced this week that its next generation of 3D NAND flash, designated G11, will enter high-volume production in the second half of 2027. The company stated that the new memory architecture will double storage density compared to its current G9 generation while reducing power consumption per bit by more than 25%.

Specific technical benchmarks show the shift from approximately 21 Gb/mm2 to 42 Gb/mm2 in triple-level-cell configuration. Input/output speeds are projected to rise by up to 50%, moving from 3,600 MT/s to 5,400 MT/s. These specifications position the new chips to serve high-capacity solid-state drives for client and data center applications, as well as emerging storage devices designed for artificial intelligence workloads that require higher bandwidth and efficiency.

A core engineering change in the G11 design is the adoption of wafer-on-wafer bonding. This process allows Micron to fabricate the NAND memory array and the peripheral circuitry on separate wafers, each optimized for its specific function, before bonding them together. While Micron has employed CMOS-under-array designs in previous generations, the bonding technique provides greater flexibility to optimize memory and logic components independently. Chinese competitor YMTC has already utilized this bonding method.

Scott DeBoer, Micron's president and chief technology and products officer, confirmed the timing of the release. He noted that the company had previously committed to introducing the technology once it became cost-effective and aligned with product specifications. "This is the right timing for that technology," DeBoer said, describing G11 as the world's most advanced NAND.

Micron indicated that G11 will feature more than 400 layers, though the exact number of active wordlines or memory decks remains undisclosed. The company stated the design will achieve an industry-leading memory cell pitch, suggesting the density increase results from a combination of additional layers and smaller cell dimensions. Further technical details are scheduled for release in 2027, closer to the start of mass production.

Beyond the immediate G11 launch, Micron outlined a roadmap focused on scaling in all three dimensions. The company is developing high-mobility materials, ultra-dense cell architectures, and more efficient data paths to improve transistor characteristics and reduce energy usage. DeBoer stated that both the industry and Micron are scaling by adding layers and shrinking cell dimensions, though specific architectural details for generations following G11 have not yet been disclosed.